1. Field of Invention
The present invention relates to a type of electrostatic protection component and its manufacturing method, and more particularly to an electrostatic protection component suitable for use in a self-aligned silicide process, and associated manufacturing method.
2. Description of Related Art
FIGS. 1A through 1F are a series of cross-sectional views showing the progression of steps in the manufacturing of a conventional electrostatic protection component.
First, referring to FIG. 1A, a first gate terminal 11 and a second gate terminal 12 are formed above a semiconductor substrate 10. After that, using the first gate terminal 11 and the second gate terminal 12 as masks, an ion implantation operation is carried out, for example, implanting N-type ions, to form first lightly doped regions 13 in the semiconductor substrate 10 on each side of the first gate terminal 11 as well as first lightly doped regions 14 in the semiconductor substrate 10 on each side of the second gate terminal 12.
Thereafter, referring to FIG. 1B, a deposition method is used to form an oxide layer 15, preferably a borophosphosilicate glass (BPSG) layer, covering the semiconductor substrate 10.
Then, referring to FIG. 1C, the oxide layer 15 is etched to form first spacers 16 on the sidewalls of the first gate terminal 11 and second spacers 17 on the sidewalls of the second gate terminal 12. Following that, using the first gate terminal 11, the first spacers 16, the second gate terminal 12 and the second spacers 17 as masks, another ion implantation operation is performed, again implanting N-type ions into the semiconductor substrate 10, to form first heavily doped regions 18 and 19 on each side of the first gate terminal 11 and the second gate terminal 12, respectively.
Next, referring to FIG. 1D, a metallic layer, for example, a titanium metal layer, is sputtered onto the surface of the semiconductor substrate 10, and then a rapid thermal processing (RTP) is applied to let the titanium metal react with the silicon above various surfaces of the semiconductor substrate 10 to form metal silicide layers 110, preferably titanium silicide layers, above the first gate terminal 11, the second gate terminal 12, and the first heavily doped regions 18 and 19. Thereafter, the residual unreacted metallic titanium layer is removed by etching.
Subsequently, referring to FIG. 1E, a photoresist layer covering the metal silicide layers 110 is formed above the first gate terminal 11 and the first heavily doped regions 18 followed by etching to remove the second spacers 17 from the second gate terminal 12. Thereafter, an ion implantation operation is performed by implanting N-type ions into the semiconductor substrate 10 to form second heavily doped regions 111 in place of the original second lightly doped regions 14 near the second gate terminal 12. The width of the second heavily doped regions 111 is about 0.1 .mu.m. After that, the metal silicide layer 110 above the first heavily doped regions 19 are removed by etching to expose the first heavily doped regions 19. The reason for establishing the second heavily doped regions 111 is to shorten the channel length below the second gate terminal 12 such that electrostatic discharging current can be more easily absorbed, and the reason for removing the metal silicide layer 110 above the first heavily doped regions 19 is to increase electrical resistance there so that a higher voltage can be reached when there is a sudden electrostatic discharge from the component, and therefore be more capable of withstanding damages resulting from the passing of a transient heavy current.
Finally, referring to FIG. 1F, an insulating layer 112, preferably a borophosphosilicate glass layer, is formed covering the semiconductor substrate 10. Then, a number of contact window openings 113 are formed by etching the insulating layer 112 and exposing the first heavily doped regions 18 and 19, for example, by forming contact windows 113a and 113b, one on each side of the second gate terminal 12, thus completing the manufacturing steps required for forming a conventional electrostatic protection component.
However, when the component dimensions are further reduced, the original designed reliability of such a conventional electrostatic protection component is difficult to maintain. For example, the distance between the second gate terminal 12 and the contact window opening 113a is preferably maintained at between 3 .mu.m to 4 .mu.m. If this distance is reduced as the size of the component is reduced, or for any other reason, current leakage can occur more easily, thereby losing part of the electrostatic protection function. In addition, the aforementioned method for manufacturing the electrostatic protection component is rather complicated and involves a lot of steps. Hence, production cost as well as production time is increased.